//------------------------------------------------------------------
//  Altera PCI testbench
//  MODULE NAME: clk_gen

//  FUNCTIONAL DESCRIPTION:
//  This file generates clock for the system                             
//  Change the pciclk_66Mhz_enable to true in the top level file         
//  to generate 66Mhz clock for the system.                              

//  This is the top level file of Altera PCI testbench

//  REVISION HISTORY:  
//  Revision 1.1 Description: No change.
//  Revision 1.0 Description: Initial Release.
//
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//  governed by the terms and conditions of the applicable Altera Reference 
//  Design License Agreement (either as signed by you or found at www.altera.com).  
//  By using this reference design file, you indicate your acceptance of such terms 
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//  not agree with such terms and conditions, you may not use the reference design 
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//  This reference design file is being provided on an �as-is� basis and as an 
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//---------------------------------------------------------------------------------------


module clk_gen (pciclk);

   parameter pciclk_66Mhz_enable  = 1'b1;

   output pciclk; 
   wire pciclk;

   reg clk; 

   always 
   begin : clk_process
      if (pciclk_66Mhz_enable)
      begin
         clk <= 1'b1 ; 
         #7; 
         clk <= 1'b0 ; 
         #8; 
      end
      else
      begin
         clk <= 1'b1 ; 
         #15; 
         clk <= 1'b0 ; 
         #15; 
      end 
   end 
   assign pciclk = clk ; 
endmodule
